Digital Communication & Information Theory

Digital Communication & Information Theory

  • September 30 2023
  • Bhimsen

VLSI Based Digital Communication projects

IEEE Digital Communication & Information Theory projects for M.Tech, B.Tech, BE, MS, MCA, BCA Students. 


1.Low complexity and area efficient  reconfigurable multimode interleaver address generator for multistandard radios

Abstract: Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is quite complex.

In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode inter leaver address generator to support multiple wireless standards. In addition, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates.

The reconfigurable address generator for various block size and modulation scheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches

2.Design and Stability Analysis of CNTFET based SRAM Cell

Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in today's technological environment. The continuous scaling of CMOS technology significantly limits the performance of 6T SRAM cell in terms of leakage power and stability. With remote chances to further improve the MOSFET technology in future, Carbon Nanotube Field Effect Transistors (CNTFETs) are being widely studied as the possible alternatives. In this paper, the conventional 6T SRAM cell is compared with CNTFET based SRAM cell.

The conventional 6T SRAM cell is designed using Cadence Virtuoso Tool in 180nm and 45nm Technology. The Verilog-A code of CNTFET for replacing nMOS and pMOS are separately simulated in Cadence Virtuoso Tool. The CNTFET based SRAM cell is technology independent. The performances are evaluated in terms of leakage power, delay and stability to show that the CNTFET based SRAM cell can successfully replace the CMOS based SRAM cell.

3.Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers

Fast Fourier Transform (FFT) is one of the most important algorithm in signal processing and communications and is used in orthogonal frequency division multiplexing (OFDM) systems. FFT are the crucial computational blocks to perform the baseband multicarrier demodulation in a MIMO OFDM system and the hardware complexity will be very high.

This paper proposes a CORDIC based reconfigurable 64 point Fast Fourier Transform which is used for various IEEE standard based WLAN receivers. The CORDIC based FFT block minimizes the hardware complexity because of the elimination of multiplier units and twiddle factors. This design has the minimal hardware and computational complexity to meet the IEEE standard. In this paper, a reconfigurable FFT has been realized based on CORDIC architecture. The coding for reconfigurable 64 point FFT has been done using VHDL under Xilinx platform. The results are verified and are found to be compatible with Virtex xc6vcx240t-2ff704.

4.A Bit-Interleaved Embedded Hamming Scheme to Correct Single-Bit and Multi-Bit Upsets for SRAM-Based FPGAs


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