---
title: VLSI Based Digital Communication & Information Theory Projects
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# Digital Communication & Information Theory
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## Digital Communication & Information Theory
- September 30 2023
- Bhimsen
- September 30 2023
- Bhimsen
## IEEE Digital Communication & Information Theory projects for M.Tech, B.Tech, BE, MS, MCA, BCA Students.
### 1.Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios
Abstract: Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is quite complex.
In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode inter leaver address generator to support multiple wireless standards. In addition, a novel MOD\_row and MOD\_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates.
The reconfigurable address generator for various block size and modulation scheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches
### 2.Design and Stability Analysis of CNTFET based SRAM Cell
Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in today's technological environment. The continuous scaling of CMOS technology significantly limits the performance of 6T SRAM cell in terms of leakage power and stability*. *With remote chances to further improve the MOSFET technology in future, Carbon Nanotube Field Effect Transistors (CNTFETs) are being widely studied as the possible alternatives. In this paper, the conventional 6T SRAM cell is compared with CNTFET based SRAM cell.
The conventional 6T SRAM cell is designed using Cadence Virtuoso Tool in 180nm and 45nm Technology. The Verilog-A code of CNTFET for replacing nMOS and pMOS are separately simulated in Cadence Virtuoso Tool. The CNTFET based SRAM cell is technology independent. The performances are evaluated in terms of leakage power, delay and stability to show that the CNTFET based SRAM cell can successfully replace the CMOS based SRAM cell*.*
### 3.Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers
Fast Fourier Transform (FFT) is one of the most important algorithm in signal processing and communications and is used in orthogonal frequency division multiplexing (OFDM) systems. FFT are the crucial computational blocks to perform the baseband multicarrier demodulation in a MIMO OFDM system and the hardware complexity will be very high.
This paper proposes a CORDIC based reconfigurable 64 point Fast Fourier Transform which is used for various IEEE standard based WLAN receivers. The CORDIC based FFT block minimizes the hardware complexity because of the elimination of multiplier units and twiddle factors. This design has the minimal hardware and computational complexity to meet the IEEE standard. In this paper, a reconfigurable FFT has been realized based on CORDIC architecture. The coding for reconfigurable 64 point FFT has been done using VHDL under Xilinx platform. The results are verified and are found to be compatible with Virtex xc6vcx240t-2ff704.
### 4.A Bit-Interleaved Embedded Hamming Scheme to Correct Single-Bit and Multi-Bit Upsets for SRAM-Based FPGAs
Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame.
This paper proposes a novel bit interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM based FPG As. This scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%.
### 5.A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction.
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core.
The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors, hence, it has a hybrid nature. Extensive simulation results are provided. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit such as delay and circuit complexity and thus applicable to integrated circuits such as FPGAs requiring secure on-chip non-volatile storage (i.e. LUTs) for multi-context configurability.
### 6.Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
In a recent paper, a method was proposed to accelerate the majority logic decoding of difference set low density parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time.
The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error-free, the average decoding time is greatly reduced. In this brief, we study the application of a similar technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step majority logic decodable.
The results obtained show that the method is also effective for EG-LDPC codes. Extensive simulation results are given to accurately estimate the probability of error detection for different code sizes and numbers of errors.
### 7.Block Inter-leaver Design for High Data Rate Wireless Networks
With increasing data rates in wireless communication, quality of service (QoS) has become a major issue. This is more with fading channels transmitting huge volumes of data. QoS is degraded by inter symbol interference (ISI) and related errors. One of the simplest and convenient techniques to overcome such errors is interleaving,
which is used efficiently in wireless applications. It has found applications for combating burst errors that creeps up in the channel during transmission. In this paper, an efficient model of a block interleaver using a hardware description language (Verilog) is proposed. The proposed technique reduces consumption of FPGA resources to a large extent, which implies low power consumption.
### 8.A Novel Reconfigurable Architecture For Generic OFDM Modulator Based On FPGA
OFDM is a special case of multi-carrier modulations, which is of great use in various wireless communications, such as DAB, DVB, HDTV, CMMB, TMMB, 802.11a. The OFDM frame structure is similar to each other. It consists of a number of OFDM symbols following the synchronizing signal with different cyclic prefix and guard interval. In this case, it is significant for researchers to implement OFDM modulator through a novel reconfigurable architecture to meet different communication standards. This paper shows how the architecture is realized on FPGA.
### 9.Implementation and Evaluation of a High-Performance MIMO Detector for Wireless LAN Systems
This paper presents the implementation and experimental evaluation of an advanced MIMO detector for wireless LAN systems. The proposed detector architecture is based on the well-known lattice-reduction aided MMSE method. Several optimizations at both algorithmic and architectural level are presented which result in an efficient VLSI design able to meet the timing requirements of a practical OFDM-based wireless LAN receiver while keeping complexity at moderate levels.
Moreover, the detector offers built-in compensation for transmitter impairments such as nonlinear power amplifier characteristics, hence providing a full and cost-effective solution for practical systems. The described solution is implemented on an FPGA-based IEEE802.11n prototype and evaluation results comparing performance of both conventional MMSE and reduced-lattice detection under several propagation scenarios are presented.
Experimental results show significantly lower error rates at the receiver for the advanced detector, or equivalently a lower number of required receiver antenna elements for a given performance target, hence resulting in lower cost, physical size and energy consumption.
### 10.Comparative analysis of different hardware decoder architectures for IEEE 802.11ad LDPC code
This paper considers the LDPC code designed for the IEEE 802.11ad WLAN standard and analyzes different architectural options for the hardware decoder. Three decoder architectures are studied that provide different tradeoffs between the throughput and the required amount of the resources for the FPGA implementation.
The standard fully parallel decoder is demonstrated to have the maximum throughput of above 6.5 Gbit/s and also the maximum hardware efficiency (a ratio of the decoder throughput to the amount of the consumed hardware logic). The layered decoder architecture allows reusing the hardware check nodes blocks between the sub-iterations to achieve 46% lower hardware resources utilization relative to the fully parallel decoder though at the expense of the 42% lower hardware efficiency and providing the throughput of 2.1 Gbit/s.
The serial-parallel decoder architecture exploits the layered and quasi-cyclic properties of the code matrix and occupies only 11% of the hardware resources needed by the fully parallel decoder but with the throughput of only 159 Mbit/s.
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